The present invention relates to a phase locked loop, and in particular, to a phase locked loop having the capability of high speed operation.
Clock recovery circuits employing PLLs (Phase Locked Loops) have become very important in the field of data communication especially for miniaturizing devices, and a variety of PLLs have been proposed and reported. Among such techniques concerning PLLs, a PLL which is provided with a frequency comparator so as to enlarge the pull-in range (pull-in frequency range) has been disclosed in a paper: xe2x80x9cA PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator ICxe2x80x9d, IEEE Journal of Solid-State Circuit, vol.26, No.10, pages 1345-1353 (October 1991).
FIG. 1 is a circuit diagram showing a conventional PLL which is disclosed in the above document. The PLL shown in FIG. 1 comprises a D-FF 70, a delay circuit 71, an EXOR circuit 72, a first phase comparator 73, a second phase comparator 74, a VCO (Voltage Controlled Oscillator) 75, a differential circuit 76, a lowpass filter 77 and a mixer 78.
An input signal is delayed by the delay circuit 71 by half the clock cycle, and the delayed input signal is supplied to the EXOR circuit 72. Meanwhile, the input signal is also supplied to the EXOR circuit 72 directly. Thereby a pulse signal is generated by the EXOR circuit 72 when data change occurs in the input signal. The pulse signal is supplied to the first phase comparator 73 and the second phase comparator 74, which compare the phase of the pulse signal with the phase of a clock signal which is generated by the VCO 75. For the comparison, the clock signal having a phase 0xc2x0 is supplied to the first phase comparator 73, and the clock signal having a phase 90xc2x0 is supplied to the second phase comparator 74. The output of the first phase comparator 73 is inputted to the differential circuit 76, and thereby a differentiated signal is supplied to the mixer 78. Meanwhile, the output of the second phase comparator 74 is directly inputted to the mixer 78. The mixer 78 multiplies the differentiated signal supplied from the differential circuit 76 and the output of the second phase comparator 74 together. The output of the mixer 78 is returned to the VCO 75 via the lowpass filter 77.
The output of the lowpass filter 77 becomes a DC voltage which is proportional to the frequency difference between the input signal and the clock signal. Therefore, a PLL provided with a frequency comparator is formed by the circuit of FIG. 1 and thereby a PLL having a wide pull-in range is realized.
If we describe the clock signal having the phase 0xc2x0 and the clock signal having the phase 90xc2x0 as A sin ((xcfx89t) and A cos ((xcfx89t) respectively, the output of the first phase comparator 73 can be described as:
B sin(dxcfx89t+dxcex8)xe2x80x83xe2x80x83(1)
and the output of the second phase comparator 74 can be described as:
B cos(dxcfx89t+dxcex8)xe2x80x83xe2x80x83(2)
where dxcfx89 is the frequency difference (angular velocity difference) between the input signal and the clock signal, and dxcex8 is the phase difference between the input signal and the clock signal.
Since the output of the first phase comparator 73 is inputted to the differential circuit 76, the output of the differential circuit 76 becomes:
dxcfx89B cos(dxcfx89t+dxcex8)xe2x80x83xe2x80x83(3).
The signals of the expressions (2) and (3) are multiplied together by the mixer 78, therefore, the output of the mixer 78 becomes:
dxcfx89B2/2xc3x97(1+cos(2(dxcfx89t+dxcex8)))xe2x80x83xe2x80x83(4).
The signal (4) can be divided into a DC component which is proportional to the frequency difference and an AC component whose frequency is twice the frequency difference between the input signal and the clock signal. Therefore, by removing the AC component by the lowpass filter 77, a VCO control voltage which is proportional to the frequency difference can be obtained. By the capability of detecting the frequency difference, a PLL which is capable of enlarging the pull-in range up to the capture range of the VCO regardless of the time constant of the lowpass filter 77 and capable of operating stably is realized.
However, the conventional PLL described above requires precision of each block or component of the PLL since the frequency difference between the clock signal and the input data signal is detected in an analog manner. For example, in cases where the precision of the differential circuit 76 is deteriorated for some reason and the 90xc2x0 phase shift is not executed by the differential circuit 76 precisely, an offset voltage occurs in the output of the mixer 78. For the offset voltage, an offset compensation has to be done from outside the PLL. Further, such a high precision circuit becomes more and more harder to manufacture as the operating frequency of the PLL becomes high, and thus stable operation of the PLL in higher frequency becomes very difficult. Therefore, a PLL having wide pull-in range and capability of high speed operation is being required today.
Further, even if the pull-in could be done against the input data signal, phase difference tends to occur between the clock signal generated by the VCO and the input data signal as the bit rate of the input data signal becomes higher. In a clock recovery circuit employing a decision circuit for executing data recognition/regeneration and outputting the recognized/regenerated data, such phase difference between the clock signal and the input data signal supplied to the decision circuit has to be eliminated, that is, phase adjustment has to be executed to the clock signal which is inputted to the decision circuit so that edges (rising edges or falling edges) of the clock signal to be used for the data recognition/regeneration by the decision circuit will come to the optimum decision point (i.e. the midpoint of each time slot of the input data signal).
Such phase adjustment used to be executed by inserting a delay circuit etc. in front of the decision circuit. However, techniques for eliminating the need of the phase adjustment have been proposed these days. Such an example of a PLL has been disclosed in a paper: xe2x80x9cA Self Correcting Clock Recovery Circuitxe2x80x9d, IEEE Journal of Lightwave Technology, vol.LT-3, No. 6, pages 1312-1314 (December 1983).
FIG. 2 is a circuit diagram showing the conventional PLL (clock recovery circuit) which is disclosed in the above document. The PLL of FIG. 2 is composed of a phase comparator 80, a filter 81 and a VCO 82. In the phase comparator 80, a first D-FF 83 and a second D-FF 84 are connected in series. The input data signal is supplied to the data input terminal D of the first D-FF 83. The output terminal Q of the first D-FF 83 is connected to the data input terminal D of the second D-FF 84, and thereby recognized/regenerated input data is outputted from the output terminal Q of the second D-FF 84. The clock terminal C of the first D-FF 83 is supplied with the clock signal from the VCO 82, and the clock terminal C of the second D-FF 84 is supplied with an inverted clock signal which is generated by inverting the clock signal from the VCO 82 by an inverter 85. The data input terminal D and the output terminal Q of the first D-FF 83 are connected to a first EXOR circuit 86, and the data input terminal D and the output terminal Q of the second D-FF 84 are connected to a second EXOR circuit 87. The outputs of the first and the second EXOR circuits 86 and 87 are supplied to an adder 88, in which the output of the first EXOR circuit 86 is inputted to the adder 88 so as to be added and the output of the second EXOR circuit 87 is inputted to the adder 88 so as to be subtracted. The output of the adder 88 is supplied to the filter 81, and the output of the filter 81 is returned to the VCO 82 as a control signal.
The PLL of FIG. 2 operates as follows. FIGS. 3 and 4 are timing charts showing the operation of the phase comparator 80 of the conventional PLL of FIG. 2, in which FIG. 3 shows a case where the phase of the clock signal (VCO OUTPUT) is behind the phase of the input data signal and FIG. 4 shows a case where the phase of the clock signal (VCO OUTPUT) is ahead of the phase of the input data signal. Incidentally, the expressions xe2x80x9cbehindxe2x80x9d and xe2x80x9cahead ofxe2x80x9d are used with respect to falling edges of the clock signal. As shown in FIG. 3(e) and FIG. 4(e), the output of the first EXOR circuit 86 becomes pulses each of which has a pulse width determined by time difference between a changing point of the input data signal (FIG. 3(a) and FIG. 4(a)) and a changing point of the clock signal (VCO OUTPUT) (FIG. 3(b) and FIG. 4(b)). Meanwhile, as shown in FIG. 3(f) and FIG. 4(f), the output of the second EXOR circuit 87 becomes pulses each of which has a pulse width of half the cycle of the clock signal.
In the case where the phase of the clock signal is behind the phase of the input data signal, the output pulse width of the first EXOR circuit 86 (FIG. 3(e)) becomes wider than that of the second EXOR circuit 87 (FIG. 3(f)), and thereby the average of the output signal of the adder 88 (FIG. 3(g)) via the filter 81 becomes a positive voltage.
On the other hand, in the case where the phase of the clock signal is ahead of the phase of the input data signal, the output pulse width of the first EXOR circuit 86 (FIG. 4(e)) becomes narrower than that of the second EXOR circuit 87 (FIG. 4(f)), and thereby the average of the output signal of the adder 88 (FIG. 4(g)) via the filter 81 becomes a negative voltage.
As described above, the average output voltage of the phase comparator 80 changes depending on the phase difference between the clock signal and the input data signal, therefore, the phase comparator 80 can correctly operate as a phase comparator. The PLL phase-locks when the average output voltage of the phase comparator 80 becomes 0, that is, when the output pulse width of the first EXOR circuit 86 becomes equal to that of the second EXOR circuit 87. At such a moment, the phase (of rising edges) of the clock signal comes to the midpoint of each time slot of the input data signal. The first D-FF 83 and the second D-FF 84 also have a function of a decision circuit. Therefore, by the above composition of the PLL, a clock recovery circuit capable of executing data recognition/regeneration at the optimum decision point of the decision circuit without phase adjustment can be realized.
However, in such a clock recovery circuit employing the conventional PLL, when the phase of the clock signal is ahead of the phase of the input data signal and the phase difference is large, the output pulse width of the first EXOR circuit 86 becomes very narrow. Therefore, the EXOR circuits 86 and 87 are required the capability of high speed operation. Generally, an EXOR circuit can output pulses of enough height and width when the output pulse width is wide enough, however, when the output pulse width becomes narrower, the output pulse amplitude tends to become smaller (depending on the operating speed of the EXOR circuit), and thereby detection of the phase difference becomes impossible. Especially, for Gb/s class signals, the phase comparator employing an IC becomes difficult, since the EXOR circuit is required operating speed of 2 to 3 times the bit rate of the signal.
It is therefore the primary object of the present invention to provide a phase locked loop having a wide pull-in frequency range and the capability of high speed operation.
Another object of the present invention is to provide a phase locked loop by which need for the phase adjustment of the clock signal in high speed operation and the effect of variations in quality of device elements are eliminated and thereby stable high speed operation is realized.
In accordance with a first aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a phase comparator, a frequency comparator and a filter. The voltage controlled oscillator, whose oscillation frequency is controlled by a control signal, generates and outputs a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. The phase comparator executes phase comparison between the first clock signal and the input data signal, and outputs the result of the phase comparison. The frequency comparator executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a second aspect of the present invention, in the first aspect, the frequency comparator is composed of digital components.
In accordance with a third aspect of the present invention, in the first aspect, the frequency comparator includes a cycle slip detection circuit and an UP/DOWN signal generation circuit. The cycle slip detection circuit samples the first clock signal in sync with changing points of the input data signal, detects change of the value of the sampled first clock signal, and outputs a detection signal when the change of the sampled first clock signal is detected. The UP/DOWN signal generation circuit judges whether the frequency of the clock signal is higher or lower than the frequency of the input data signal when the cycle slip detection circuit outputted the detection signal based on a sampled data of the second clock signal which is obtained by sampling the second clock signal in sync with a changing point of the input data signal, outputs a DOWN signal for decreasing the oscillation frequency of the voltage controlled oscillator when the frequency of the clock signal is judged to be higher than that of the input data signal, and outputs an UP signal for increasing the oscillation frequency of the voltage controlled oscillator when the frequency of the clock signal is judged to be lower than that of the input data signal.
In accordance with a fourth aspect of the present invention, in the third aspect, the cycle slip detection circuit includes a first sample hold circuit whose clock terminal is supplied with the input data signal and whose data input terminal is supplied with the first clock signal, a second sample hold circuit whose clock terminal is supplied with the input data signal and whose data input terminal is supplied with the output of the first sample hold circuit, and an EXOR circuit which is supplied with the outputs of the first sample hold circuit and the second sample hold circuit.
In accordance with a fifth aspect of the present invention, in the fourth aspect, the UP/DOWN signal generation circuit includes a third sample hold circuit whose data input terminal is supplied with the second clock signal and whose clock terminal is supplied with the input data signal, a first AND circuit which is supplied with the outputs of the first sample hold circuit and the third sample hold circuit, a second AND circuit which is supplied with the outputs of the second sample hold circuit and the third sample hold circuit, a first D-FF whose data input terminal is supplied with the output of the first AND circuit and whose clock terminal is supplied with the output of the EXOR circuit, and a second D-FF whose data input terminal is supplied with the output of the second AND circuit and whose clock terminal is supplied with the output of the EXOR circuit. Thereby the DOWN signal is outputted by the first D-FF and the UP signal is outputted by the second D-FF.
In accordance with a sixth aspect of the present invention, in the fourth aspect, the UP/DOWN signal generation circuit includes a third sample hold circuit whose data input terminal is supplied with the second clock signal and whose clock terminal is supplied with the input data signal, a first AND circuit which is supplied with the outputs of the first sample hold circuit and a second D-FF, a second AND circuit which is supplied with the outputs of the second sample hold circuit and a first D-FF, a third AND circuit which is supplied with the outputs of the EXOR circuit and the third sample hold circuit, the first D-FF whose data input terminal is supplied with the output of the first AND circuit and whose clock terminal is supplied with the output of the third AND circuit, and the second D-FF whose data input terminal is supplied with the output of the second AND circuit and whose clock terminal is supplied with the output of the third AND circuit. Thereby the DOWN signal is outputted by the first D-FF and the UP signal is outputted by the second D-FF.
In accordance with a seventh aspect of the present invention, in the fourth aspect, each sample hold circuit of the cycle slip detection circuit includes a first latch, a second latch and a selector. The data input terminal of the first latch is connected with the data input terminal of the sample hold circuit, and the clock terminal of the first latch is connected with the clock terminal of the sample hold circuit. The first latch holds data at its data input terminal from the moment when a rising edge is supplied to its clock terminal till the moment when a falling edge is supplied to the clock terminal. The data input terminal of the second latch is connected with the data input terminal of the sample hold circuit, and the inverted clock terminal of the second latch is connected with the clock terminal of the sample hold circuit. The second latch holds data at its data input terminal from the moment when a falling edge is supplied to its inverted clock terminal till the moment when a rising edge is supplied to the inverted clock terminal. The input terminals of the selector are supplied with the outputs of the first latch and the second latch, and the selection control terminal of the selector is supplied with the input data signal which is supplied to the clock terminal of the sample hold circuit. The selector selects and outputs the output of the first latch or the output of the second latch depending on the logical value of the input data signal which is supplied to the selection control terminal.
In accordance with an eighth aspect of the present invention, in the seventh aspect, the selector selects and outputs the output of the first latch when the logical value of the selection control terminal is xe2x80x9c1xe2x80x9d, and selects and outputs the output of the second latch when the logical value of the selection control terminal is xe2x80x9c0xe2x80x9d.
In accordance with a ninth aspect of the present invention, in the fourth aspect, each sample hold circuit of the cycle slip detection circuit includes a D-FF whose data input terminal is connected with the data input terminal of the sample hold circuit and whose clock terminal is connected with the clock terminal of the sample hold circuit.
In accordance with a tenth aspect of the present invention, in the first aspect, the filter includes a first filter which is provided corresponding to the phase comparator so as to remove high frequency components of the output of the phase comparator, a second filter which is provided corresponding to the frequency comparator so as to remove high frequency components of the output of the frequency comparator, and an adder for adding the outputs of the first filter and the second filter together.
In accordance with an eleventh aspect of the present invention, in the third aspect, the filter includes a first filter which is provided corresponding to the phase comparator so as to remove high frequency components of the output of the phase comparator, a second filter which is provided corresponding to the frequency comparator so as to remove high frequency components of the output of the frequency comparator, and an adder for adding the outputs of the first filter and the second filter together. The second filter generates a voltage for increasing the oscillation frequency of the voltage controlled oscillator when the UP signal is supplied from the frequency comparator, and generates a voltage for decreasing the oscillation frequency of the voltage controlled oscillator when the DOWN signal is supplied from the frequency comparator.
In accordance with a twelfth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator and a filter. The voltage controlled oscillator generates and outputs a clock signal. The oscillation frequency of the voltage controlled oscillator is controlled by a control signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with rising edges of the clock signal. The phase comparator executes phase comparison between the clock signal and the input data signal by sampling the input data signal in sync with falling edges of the clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The filter removes high frequency components from the output of the phase comparator and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a thirteenth aspect of the present invention, in the twelfth aspect, the phase comparator is composed of digital components.
In accordance with a fourteenth aspect of the present invention, in the twelfth aspect, the phase comparator includes a first inverter, a D-FF, a second inverter, a third inverter, a first latch, a second latch and a selector. The first inverter inverts the clock signal which is outputted by the voltage controlled oscillator. The D-FF samples the input data signal in sync with rising edges of the clock signal which has been inverted by the first inverter and outputs the sampled data. The second inverter inverts the output of the D-FF. The third inverter inverts the output of the decision circuit. The first latch samples the output of the D-FF in sync with rising edges of the output of the decision circuit, and holds the sampled data while the output of the decision circuit remains xe2x80x9c1xe2x80x9d. The second latch samples the output of the D-FF which has been inverted by the second inverter in sync with rising edges of the output of the decision circuit which has been inverted by the third inverter, and holds the sampled data while the output of the decision circuit which has been inverted by the third inverter remains xe2x80x9c1xe2x80x9d. The selector selects and outputs the output of the first latch when the output of the decision circuit is xe2x80x9c1xe2x80x9d, and selects and outputs the output of the second latch when the output of the decision circuit is xe2x80x9c0xe2x80x9d.
In accordance with a fifteenth aspect of the present invention, in the twelfth aspect, the decision circuit and the phase comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.
In accordance with a sixteenth aspect of the present invention, in the twelfth aspect, the phase comparator includes a first inverter, a first D-FF and a second D-FF. The first inverter inverts the clock signal which is outputted by the voltage controlled oscillator. The first D-FF samples the input data signal in sync with rising edges of the clock signal which has been inverted by the first inverter and outputs the sampled data. The second D-FF samples the output of the first D-FF in sync with rising edges of the output of the decision circuit, and thereby executes phase comparison between the clock signal and the input data signal.
In accordance with a seventeenth aspect of the present invention, in the sixteenth aspect, the second D-FF is supplied with the output of the first D-FF to its data input terminal via a second inverter, and is supplied with the output of the decision circuit to its clock terminal via a third inverter.
In accordance with an eighteenth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator and a filter. The voltage controlled oscillator generates and outputs a clock signal. The oscillation frequency of the voltage controlled oscillator is controlled by a control signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with falling edges of the clock signal. The phase comparator executes phase comparison between the clock signal and the input data signal by sampling the input data signal in sync with rising edges of the clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The filter removes high frequency components from the output of the phase comparator and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a nineteenth aspect of the present invention, in the eighteenth aspect, the phase comparator is composed of digital components.
In accordance with a twentieth aspect of the present invention, in the eighteenth aspect, the phase comparator includes a first inverter, a D-FF, a first inverter, a second inverter, a first latch, a second latch and a selector. The first inverter inverts the clock signal which is outputted by the voltage controlled oscillator. The D-FF samples the input data signal in sync with rising edges of the clock signal and outputs the sampled data. The first inverter inverts the output of the D-FF. The second inverter inverts the output of the decision circuit. The first latch samples the output of the D-FF in sync with rising edges of the output of the decision circuit, and holds the sampled data while the output of the decision circuit remains xe2x80x9c1xe2x80x9d. The second latch samples the output of the D-FF which has been inverted by the first inverter in sync with rising edges of the output of the decision circuit which has been inverted by the second inverter, and holds the sampled data while the output of the decision circuit which has been inverted by the third inverter remains xe2x80x9c1xe2x80x9d. The selector selects and outputs the output of the first latch when the output of the decision circuit is xe2x80x9c1xe2x80x9d, and selects and outputs the output of the second latch when the output of the decision circuit is xe2x80x9c0xe2x80x9d.
In accordance with a twenty-first aspect of the present invention, in the eighteenth aspect, the decision circuit and the phase comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.
In accordance with a twenty-second aspect of the present invention, in the eighteenth aspect, the phase comparator includes a first D-FF and a second D-FF. The first D-FF samples the input data signal in sync with rising edges of the clock signal and outputs the sampled data. The second D-FF samples the output of the first D-FF in sync with rising edges of the output of the decision circuit, and thereby executes phase comparison between the clock signal and the input data signal.
In accordance with a twenty-third aspect of the present invention, in the twenty-second aspect, the second D-FF is supplied with the output of the first D-FF to its data input terminal via a first inverter, and is supplied with the output of the decision circuit to its clock terminal via a second inverter.
In accordance with a twenty-fourth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator, a frequency comparator and a filter. The voltage controlled oscillator, whose oscillation frequency is controlled by a control signal, generates and outputs a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with rising edges of the first clock signal. The phase comparator executes phase comparison between the first clock signal and the input data signal by sampling the input data signal in sync with falling edges of the first clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The frequency comparator executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a twenty-fifth aspect of the present invention, in the twenty-fourth aspect, the decision circuit, the phase comparator and the frequency comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.
In accordance with a twenty-sixth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator, a frequency comparator and a filter. The voltage controlled oscillator, whose oscillation frequency is controlled by a control signal, generates and outputs a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with falling edges of the first clock signal. The phase comparator executes phase comparison between the first clock signal and the input data signal by sampling the input data signal in sync with rising edges of the first clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The frequency comparator executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a twenty-seventh aspect of the present invention, in the twenty-sixth aspect, the decision circuit, the phase comparator and the frequency comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.